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data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 8V34S204 8V34S204 revision 1 6/17/14 1 ?2014 integrated device technology, inc. general description the 8V34S204 is a differential 1:4 lvds fanout buffer with a 2:1 input multiplexer. the device accepts dc to 250mhz clock and data signals and is designed for 1hz clock /1pps, 2khz and 8khz signal distribution. controlled by the input mode selection pin, the differential input stages accept both rectangular or sinusoidal signals. the 8V34S204 also provides level translated lvcmos/lvttl outputs which are copies of the individual differential inputs clka and clkb. the propagation delay of the device is very low, providing an ideal solution for clock distribution circuits with tight phase alignment requirements. the multiplexer select pin (sel) allows to select one out of two input signals, which is copied to the four differential outputs. features ? designed for 1pps, 2khz, 8khz and 10mhz gps clock signal distribution ? high speed 1:4 lvds fanout buffer ? four differential lvds output pairs ? 2:1 input multiplexer ? two selectable differential inputs accept lvds and lvpecl signals ? accepts rectangular and sinusoidal input signals ? two input monitoring outputs (lvcmos) ? max output frequency: 250mhz ? additive phase jitter, rms; 12khz to 20mhz: = 65fs at 156.25mhz (typical) ? part-to-part skew: 200ps (maximum) ? propagation delay (differential outputs): 350ps (typical) ? full 2.5v and 3.3v voltage supply ? -40c to 85c ambient operating temperature ? lead-free 24-lead vfqfn (rohs 6/6) packaging block diagram pin assignment 24-lead vfqfn 4mm x 4mm x 0.9mm nl package top view pulldown pullup/pulldown clka nclka pulldown pullup/pulldown clkb nclkb pulldown sel q0 nq0 q1 nq1 q2 nq2 q3 nq3 0 (default) 1 qa qb mode pulldown svs pulldown
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 2 revision 1 6/17/14 pin description and pin characteristic tables table 1. pin descriptions 1 note: 1. pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1 clka input pulldown non-inverting differential clock input. 2 nclka input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 3 mode input pulldown input mode pin. see table 3b. lvcmos/lvttl interface levels. 4 sel input pulldown input selection pin. see table 3a. lvcmos/lvttl interface levels. 5 clkb input pulldown non-inverting differential clock input. 6 nclkb input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 7 svs input pulldown supply voltage select. see table 3c. lvcmos/lvttl interface levels. 8v ddo_b power output supply pin for the qb output. 9 qb output single-ended output clock. lvcmos/lvttl interface levels. 10 gnd power power supply ground. 11 v dd power power supply pins for the device core. 12 q0 output differential output pair. lvds interface levels. 13 nq0 output differential output pair. lvds interface levels. 14 q1 output differential output pair. lvds interface levels. 15 nq1 output differential output pair. lvds interface levels. 16 q2 output differential output pair. lvds interface levels. 17 nq2 output differential output pair. lvds interface levels. 18 q3 output differential output pair. lvds interface levels. 19 nq3 output differential output pair. lvds interface levels. 20 v dd power power supply pins for the device core. 21 gnd power power supply ground. 22 qa output single-ended output clock. lvcmos/lvttl interface levels. 23 v ddo_a power output supply pin for the qa output. 24 gnd power power supply ground.
c in input capacitance mode, sel, svs 2 pf r pulldown pulldown resistor 50 k? ? 5% 24 ? 5% 28 ?
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 4 revision 1 6/17/14 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) continuous current surge current outputs, i o (lvcmos) 10 ma 15 ma -0.5v to v dd + 0.5v maximum junction temperature, t j, max 125c storage temperature, t stg -65 ? ?
8V34S204 data sheet revision 1 6/17/14 5 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications i il input low current mode, sel, svs v dd = 3.465v, v in = 0v -10 a v oh output high voltage qa, qb i oh = -8ma 2.6 v v ol output low voltage qa, qb i ol = 8ma 0.5 v table 4c. lvcmos/lvttl dc characteristics, v dd =v ddo_a =v ddo_b , 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units table 4d. lvcmos/lvttl dc characteristics, v dd =v ddo_a =v ddo_b , 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage 1.8 v dd + 0.3 v v il input low voltage -0.3 0.6 v i ih input high current mode, sel, svs v dd =v in = 2.625v 150 a i il input low current mode, sel, svs v dd = 2.625v, v in = 0v -10 a v oh output high voltage qa, qb i oh = -8ma 1.8 v v ol output low voltage qa, qb i ol = 8ma 0.5 v table 4e. differential dc characteristics, v dd = 3.3v 5% or v dd = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clka, clkb, nclka, nclkb v dd =v in = 3.465v or 2.625v 150 a i il input low current clka, clkb v dd = 3.465v or 2.625v, v in = 0v -10 a nclka, nclkb v dd = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 1 note: 1. v il should not be less than -0.3v and v ih should not be higher than v dd . 0.15 1.3 v v cmr common mode input voltage 1 2 note: 2. common mode input voltage is defined at the crosspoint. 1v dd ?(v pp /2) v table 4f. lvds differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 390 454 mv ' v od v od magnitude change 50 mv v os offset voltage 1.05 1.2 1.375 v ' v os v os magnitude change 50 mv
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 6 revision 1 6/17/14 ac electrical characteristics f out output frequency 250 mhz ? ? ? ?
8V34S204 data sheet revision 1 6/17/14 7 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications table 6. characteristics for 1pps operation, v dd = 3.3v 5% or v dd = 2.5v 5%, ta = -40c to 85c 1234 note: 1. 1pps (one pulse per second) signals are defined as repetitive pulses with a rate (period) of 1hz. the positive input pulse width may vary. the active signal edge is the rising edge. parameters in this table are characterized for a positive input pulse width of 100ns, 100ms and 500ms; all device interfaces are dc-coupled. parameters are defined in accordance with itu-t g.703 amendment 1 - specifications for the physical layer of the itu-t g8271/y.1366 time synchronization interfaces. note: 2. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note: 3. t pd ,t sk(o) ,t sk(p) and t sk(p) parameters of differential signals are referenced to the crosspoint. note: 4. differential outputs for 1pps signal transmission are terminated balanced 100 : according to the lvds output load test circuit figures. the dedicated 1pps outputs are the differential outputs q0-q3. symbol parameter test conditions minimum typical maximum units t input and output pulse period 1 s t p positive or negative pulse width 100 ns t pd propagation delay; clkx/nclkx to qx/nqx 325 650 ps tsk (p) pulse width distortion clkx/nclkx to qx/nqx 55 300 ps tsk (o) output skew 5 note: 5. this parameter is defined in accordance with jedec standard 65. qx/nqx to qy/nqy 325 ps tsk (pp) part-to-part skew 6 note: 6. defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. each device uses the same type of input. 350 ps t r /t f output rise/fall time 10% to 90% 50 150 350 ps
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 8 revision 1 6/17/14 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. noise power (dbc/hz) offset frequency (hz) as with most timing specifications, phase noise measurements have issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. measured using an rohde & schwarz sma100 as the input source.
8V34S204 data sheet revision 1 6/17/14 9 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications parameter measurement information 2.5v lvds output load test circuit 2.5v core/2.5v lvcmos output load test circuit differential input level 3.3v lvds output load test circuit 3.3v core/3.3v lvcmos output load test circuit part-to-part skew v dd scope qx gnd -1.255% 1.25v5% v dd v ddo_a v ddo_b v dd gnd v cmr cross points v pp nclk[a:b] clk[a:b] scope qx nqx 3.3v5% power supply +? float gnd v dd scope qx gnd -1.65v5% 1.65v5% v dd v ddo_a v ddo_b t sk(pp) part 1 part 2 nqx qx nqy qy
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 10 revision 1 6/17/14 parameter measurement information, continued lvds output skew differential propagation delay lvcmos output rise/fall time lvcmos output skew propagation delay lvds output rise/fall time nqx qx nqy qy t pd nclk[a:b] clk[a:b] nqx qx 20% 80% 80% 20% t r t f q[a:b] t sk(o) v ddo_x 2 v ddo_x 2 qx qy t pd v ddo_x 2 nclk[a:b] clk[a:b] q[a:b] 20% 80% 80% 20% t r t f v od nq[0:3] q[0:3]
8V34S204 data sheet revision 1 6/17/14 11 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications parameter measurement information, continued differential pulse skew differential output voltage setup mux isolation pulse skew offset voltage setup t plh t phl tsk(p)= |t phl -t plh | nclk[a:b] clk[a:b] nqx qx amplitude (db) a0 spectrum of output signal q mux _isolation =a0?a1 (fundamental) frequency mux selects other input mux selects active input clock signal a1 t plh t phl tsk(p)= |t phl -t plh | v ddo_x 2 v ddo_x 2 nclk[a:b] clk[a:b] q[a:b]
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 12 revision 1 6/17/14 applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 =v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a differential input to accept single-ended levels
8V34S204 data sheet revision 1 6/17/14 13 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 3.3v differential clock input interface the clk /nclk accepts lvds, lvpecl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. ta b l e 2 a to ta bl e 2 c show interface examples for the clk/nclk input with built-in 50 ?
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 14 revision 1 6/17/14 2.5v differential clock input interface the clk /nclk accepts lvds, lvpecl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 3a to figure 3c show interface examples for the clk/nclk input with built-in 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
8V34S204 data sheet revision 1 6/17/14 15 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullup resistors; additional resistance is not required but can be added for additional protection. a 1k : resistor can be used. clk/nclk input for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k : resistor can be tied from clk to ground. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 : across. if they are left floating there should be no trace attached.
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 16 revision 1 6/17/14 lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? ? ? ? figure 4a can be used with either type of output structure. figure 4b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds driver z o ? ?
8V34S204 data sheet revision 1 6/17/14 17 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications power considerations ? lvds outputs this section provides information on power dissipation and junction temperature for the 8V34S204 for all outputs that are configured to lvds (lev_sel = 0). equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8V34S204 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the f ollowing is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. the maximum current at 85c is as follows: i dd = 108ma i ddoa = 4ma i ddob = 4ma ? power (core, lvds) max =v dd_max *(i dd_max +i ddoa_max +i ddob_max ) = 3.465v * (108ma + 4ma + 4ma) = 401.94mw lvcmos output power dissipation ?dynamic power dissipation at 200mhz power (250mhz) = c pd * frequency * (v ddox_max ) 2 = 6pf * 250mhz * (3.465v) 2 = 18.01mw per output total cmos powe r=2*18.01mw = 36.02mw total power_ max = 401.94mw + 36.02mw = 437.96mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maxim um recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ? ? ? ?
meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 62.2c/w 54.4c/w 48.8c/w 8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 18 revision 1 6/17/14 reliability information transistor count the transistor count for the 8V34S204 is: 492 table 8. ? ?
8V34S204 data sheet revision 1 6/17/14 19 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 24-lead vfqfn package information
8V34S204 data sheet 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications 20 revision 1 6/17/14 24-lead vfqfn package information
8V34S204 data sheet revision 1 6/17/14 21 1:4 lvds fanout buffer with 2-input multiplexer for 1pps applications ordering information table 9. ordering information part/order number marking package shipping packaging temperature 8V34S204nlgi s204gi ?lead-free? 24-lead vfqfn tray -40 q cto85 q c 8V34S204nlgi8 s204gi ?lead-free? 24-lead vfqfn tape & reel -40 q cto85 q c
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